Recent advances in the miniaturization of integrated circuits have led to smaller wafer areas made available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet even as the "footprint" (area of a silicon wafer allotted Individual memory cells) shrinks, the storage node (capacitor) must maintain a certain minimum charge storage capacity, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge storage per unit area of the wafer. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the wafer area occupied by the cell.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interelectrode dielectric material is deposited between two conductive layers, which form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance, C=.epsilon..epsilon..sub.0 A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, .epsilon..sub.0 is the vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance include the use of new materials characterized by high dielectric constants.
Other techniques concentrate on increasing the effective surface area ("A") of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and capacitor dielectric conform. For example, U.S. Pat. No. 5,340,765, issued Aug. 23, 1994 to Dennison et al. and assigned to the assignee of the present invention, discloses a process for forming a capacitor structure resembling a cylindrical container. More complex structures, such as the container-within-container and multiple pin structures disclosed in U.S. Pat. No. 5,340,763, issued Aug. 23, 1994 to Dennison, may further increase electrode surface area and allow the extension of conventional fabrication materials to future generation memory devices.
FIGS. 1-3 illustrate the fabrication of a simple container in the context of a dynamic random access memory (DRAM) cell. FIG. 1 illustrates a partially fabricated memory cell within an integrated circuit, representing a starting point for the preferred embodiments of the present invention. A conductive plug 10 between neighboring word lines 12, usually comprising polysilicon, forms electrical contact with an active area 14 of a semiconductor substrate 16, such as a silicon wafer. A planarized insulating layer 18, generally an oxide in the form of borophosphosilicate glass (BPSG), surrounds the word lines 12, the plug 10 is formed within an opening through the insulating layer 18, and a structural layer 22 overlies the insulating layer 18 in turn. The structural layer 22 may also comprise a layer of BPSG. A container 24 is then opened within the structural layer 22, thereby exposing the conductive plug 10.
The container 24 is generally etched anisotropically through a mask, resulting in a cylindrical container 24 with vertical sidewalls, in accordance with conventional integrated circuit contact formation. (FIG. 1 is a schematic cross-section which does not show the back wall of the container. In reality, the container resembles a three-dimensional cylinder.) As dimensions continue to be scaled below the submicron level, the container shrinks in the horizontal dimension. The height of the container, however, should at least remain constant. More likely, the container height must be increased in order to maintain the capacitance of previous-generation memory cells. In other words, the aspect ratio of containers increases as circuitry becomes more densely packed. The illustrated container 24 is thus characterized by a diameter of between about 5,000 .ANG. and 6,000 .ANG. (0.5-0.6 micron), a depth of about 10,000 .ANG., and thus an aspect ratio greater than 1.0. These dimensions are typical of 4 Mbit to 64 Mbit DRAM arrays. Note that FIG. 1 and the drawings to follow are not drawn to scale.
Referring now to FIG. 2, a conductive layer 26 is then deposited over the structural layer 22. The conductive layer 26, which lines the inside surfaces of the container 24 and includes horizontal portions 27 overlying the unetched structural layer 22, forms the structural basis for the capacitor bottom electrode to be further defined in later process steps. The conductive layer 26 conventionally takes the form of a polysilicon layer 26 due to advantages in deposition of polysilicon. While sputtered metals may demonstrate greater conductivity than polysilicon, they cannot provide conformal coverage of the container 24, especially where the aspect ratio is greater than about 1.0. Non-conformal metal coverage results in unsatisfactory container structures, particularly due to high resistivity at thin portions. Additionally, sputtered metal builds very quickly at the lip of the container, leaving little room for later-deposited layers such as the capacitor dielectric and the top electrode layers, and may even lead to closure of the container mouth and keyhole formation. With increasing densities of integrated circuitry, it has become vitally important that capacitor electrode layers have uniform thickness to ensure reliable memory cell operation.
The polysilicon layer 26, on the other hand, may be deposited by low pressure chemical vapor deposition (LPCVD), resulting in controlled, conformal coverage of the container 24 surfaces. The polysilicon 26 should be doped to lower access resistance and decrease the charge depletion width in the bottom plate, thus increasing capacitance and access speed. For example, the polysilicon 26 may be diffusively doped with phosphorus from solid source P.sub.2 O.sub.5, it may be doped with implanted dopants, or in-situ doped by flowing phosphine gas along with the silicon source gas (e.g., silane) during chemical vapor deposition of the polysilicon layer 26. Heavily doping the polysilicon 26, however, increases polysilicon deposition time. Nevertheless, due to advantages in achieving uniformly thick layers, polysilicon remains the standard material for folding electrode structures.
Referring now to FIG. 3, the horizontal portions 27 of the polysilicon layer 26 have been removed by a planarization step, such as chemical mechanical planarization (CMP), for isolation of the various memory cells in the array. A polysilicon container 28, which is to serve as a bottom electrode for the cell capacitor, is left in contact with the polysilicon plug 10. An inside surface 30 of the container 28 is available for charge storage during circuit operation. For other known process flows, the outside surface may also contribute to capacitance by removal of the structural layer. The capacitor dielectric and top electrode may then be successively deposited.
As shown in FIG. 4, electrode surface area may also be increased by providing a high surface area microstructure for the electrode surface. One class of methods for providing a microstructure for electrode surfaces involves texturizing a conductive layer by formation of hemispherical grained (HSG) silicon. HSG silicon may be formed by various methods known in the art, including low pressure CVD (LPCVD) and silicon deposition followed by vacuum anneal under specified temperature and pressure conditions. The container 24 of FIG. 1 is lined with a polysilicon layer 35, similar to the polysilicon 26 of FIG. 2, and an HSG silicon layer 36 is formed over the polysilicon layer 35. A planarization step may be performed after the HSG silicon layer 36 has been formed, for electrical isolation of the memory cells in an array, leaving a container similar to that of FIG. 3 but with a textured interior surface. The cell dielectric and top electrode would then be deposited conformally thereupon.
HSG silicon may increase the electrode surface area of any capacitor configuration, and may also be formed after planarization, for example, or after removal of the structural layer for process flows designed to expose the outside surfaces of the container as well. Generally, however, the rough surface is formed prior to the isolation step, as illustrated, thus avoiding additional isolation etch steps following HSG formation.
As apparent from FIG. 4, the bottom electrode surface follows the contours of individual hemispherical grains 37 of the HSG silicon 36 protruding between 300 .ANG. and 600 .ANG. above the polysilicon layer 35, providing a considerably greater surface for the bottom electrode than the smooth polysilicon layer 35 alone. Formation of taller grains 37, or increased "bump height," would tend to even further increase electrode surface area and cell capacitance. Hence, it would be advantageous to employ a thicker layer of HSG silicon.
At the same time, however, the limited volume within the container 34 puts severe constraints on the thickness of layers lining the container 34. The polysilicon layer 35 underlying the HSG silicon 36 serves as a conductive substrate, required to ensure electrical connection of individual hemispherical grains 37. Typically, the thickness of the polysilicon layer 35 is between about 500 .ANG. and 1,000 .ANG., occupying a substantial volume of the memory cell which may otherwise have been available for taller HSG silicon grains 37.
Moreover, as the packing density for DRAM arrays increases and cell dimensions are scaled down further, the polysilicon substrate below HSG silicon layers must still maintain low access resistance by maintaining thicknesses of over 300 .ANG.. Accordingly, with current fabrication processes, bump height of the HSG silicon layer 36 must be lowered to make room for the cell dielectric and top electrode. As a result, DRAM cells of current and future generations cannot take full advantage of potential further increases in surface area from thicker HSG silicon layers. In other words, cell capacitance is limited by a lack of interior volume within the cell.
A need therefore exists to increase the interior volume available within a memory cell capacitor structure of a given outside diameter.